1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package and method of fabricating the same.
2. Description of Related Art
Stacked-die semiconductor packaging technology is used to pack two or more semiconductor chips in a stacked manner in one single package unit, so as to allow one single package unit to be capable of offering a doubled level of functionality or data storage capacity (note that the term xe2x80x9csemiconductor diexe2x80x9d is synonymous to the term xe2x80x9csemiconductor chipxe2x80x9d). Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer an increased data storage capacity.
A conventional type of stacked-die semiconductor packaging technology is based on WB-FC-BGA (Wire-Bonded and Flip-Chip Ball Grid Array) architecture to pack a pair of semiconductor chips in a stacked manner over a BGA substrate, which is characterized in that the underlying chip is electrically coupled to the substrate through flip-chip (FC) technology, while the overlying chip is electrically coupled to the same substrate through wire-bonding (WB) technology.
FIG. 1 shows a schematic sectional diagram of a conventional stacked-die BGA package that is based on the WB-FC-BGA architecture. As shown, this stacked-die BGA package includes: (a) a substrate 100 having a front surface 100a and a back surface 100b; (b) a first semiconductor chip 110 having an active surface 110a and an inactive surface 110b, and whose active surface 110a is bonded and electrically coupled to the front surface 100a of the substrate 100 through flip-chip (FC) technology; (c) a second semiconductor chip 120 having an active surface 120a and an inactive surface 120b, and whose inactive surface 120b is adhered by means of an adhesive layer 121 to the inactive surface 110b of the first semiconductor chip 110; (d) a plurality of bonding wires 140, such as gold wires, which are routed from the active surface 120a of the second semiconductor chip 120 down to the front surface 100a of the substrate 100, for electrically coupling the second semiconductor chip 120 to the substrate 100; (e) an encapsulation body 150 for encapsulating the two stacked chips 110, 120 over the substrate 100; and (i) a ball grid array 160 implanted on the back surface 100b of the substrate 100.
One drawback to the forgoing stacked-die BGA package structure, however, is that the two stacked chips 110, 120 would have a poor heat-dissipation capability since no additional heat-dissipation means is provided. This would make the heat produced by the stacked chips 110, 120 during operation to accumulate therebetween Moreover, since the heat produced by the first semiconductor chip 110 would be conducted to the second semiconductor chip 120, it would cause the second semiconductor chip 120 to accumulate more heat that would make the second semiconductor chip 120 more likely damaged due to thermal stress.
FIG. 2 shows a schematic sectional diagram of a thermally-enhanced version of the stacked-die BGA package of FIG. 1. As shown, this stacked-die BGA semiconductor package is substantially identical in structure as that shown in FIG. 1, which also includes: (a) a substrate 200 having a front surface 200a and a back surface 200b; (b) a first semiconductor chip 210 having an active surface 210a and an inactive surface 210b, and whose active surface 210a is electrically coupled to the front surface 200a of the substrate 200 through FC technology, (c) a second semiconductor chip 220 having an active surface 220a and an inactive surface 220b, and whose inactive surface 220b is adhered by means of an adhesive layer 221 to the inactive surface 210b of the first semiconductor chip 210; (d) a plurality of bonding wires 240, which are routed from the active surface 220a of the second semiconductor chip 220 down to the front surface 200a of the substrate 200, for electrically coupling the second semiconductor chip 220 to the substrate 200; (e) an encapsulation body 250 for encapsulating the two stacked chips 210, 220 over the substrate 200; and (f) a ball grid array 260 implanted on the back surface 200b of the substrate 200. To enhance its heat dissipation capability, a heat spreader 230 is mounted over the substrate 200. The heat spreader 230 is substantially U-shaped in cross section having a support portion 231 and an overhead portion 232, with the support portion 231 being supported on the substrate 200 and the overhead portion 232 being positioned above the two stacked chips 210, 220. This allows the heat produced by the two stacked chips 210, 220 to be conducted first to the capsulant between the second semiconductor chip 200 and the heat spreader 230, and onwards through the heat spreader 230 to the outside atmosphere. Therefore, the stacked-die BGA package of FIG. 2 is better in heat-dissipation capability than the prior art of FIG. 1.
The forgoing package structure of FIG. 2, however, has the following drawbacks. First, since the heat spreader 230 is not in direct contact with the inactive surfaces 210b, 220b of the packaged chips 210, 220, it would result in a poor heat-dissipation capability. Second, since there are no grounding plane on the back side of each of the two packaged chips, it would result in a poor grounding effect and thereby a poor electrical performance to the packaged chips,
Related patents, include, for example, the U.S. Pat. No. 5,726,079 entitled xe2x80x9cTHERMALLY ENHANCED FLIP CHIP PACKAGE AND METHOD OF FORMINGxe2x80x9d; the U.S. Pat. No. 5,909,057 entitled xe2x80x9cINTEGRATED HEAT SPREADER/STIFFENER WITH APERTURES FOR SEMICONDUCTOR PACKAGExe2x80x9d; and the U.S. Pat. No. 5,815,372 entitled xe2x80x9cPACKAGING MULTIPLE DIES ON A BALL GRID ARRAY SUBSTRATExe2x80x9d; to name just a few.
The U.S. Pat. No. 5,726,079 discloses an advanced semiconductor packaging technology for the fabrication of a FC-BGA package, while the U.S. Pat. No. 5,909,057 discloses another semiconductor packaging technology for the fabrication of a thermally-enhanced FC-BGA package. None of these two patents, however, teach a solution to the above-mentioned problems of the stacked-die BGA package structure depicted in FIG. 1 and FIG. 2.
The U.S. Pat. No. 5,815,372 discloses a semiconductor packaging technology for the fabrication of a stacked-die BGA package based on WB-FC-BGA architecture. One drawback to this patent, however, is that since its architecture is similar to the one depicted in FIG. 1, it nevertheless has the problem of a poor heat-dissipation capability as mentioned above.
It is therefore an objective of this invention to provide a new stacked-die BGA semiconductor packaging technology that allows the chip-produced heat to be dissipated directly to the outside atmosphere.
It is another objective of this invention to provide a new stacked-die BGA semiconductor packaging technology that can provide a grounding plane to the packaged chips, so as to help enhance the electrical performance of the packaged chips.
In accordance with the foregoing and other objectives, the invention proposes a new semiconductor packaging technology for the fabrication of a stacked-die BGA semiconductor package.
By the semiconductor packaging technology according to the invention, a first semiconductor chip is mounted over a substrate through flip-chip (FC) technology; and then a heat spreader is mounted over the first semiconductor chip. The heat spreader has a support portion and an overhead portion formed with a plurality of wire-routing openings; wherein the heat spreader is mounted in such a manner that the support portion is supported on the front surface of the substrate, while the overhead portion is abutted on the inactive surface of the first semiconductor chip. Next, a second semiconductor chip is mounted over the overhead portion of the heat spreader. After this, a plurality of bonding wires are routed from the active surface of the second semiconductor chip through the wire-routing openings in the overhead portion of the heat spreader down to the front surface of the substrate, for electrically coupling the second semiconductor chip to the substrate.
Compared to the prior art, the invention has the following advantages. First, since the heat spreader is in direct contact with both of the two packaged chips, it allows an increased heat-dissipation capability as compared to the prior art. Second, since the overhead portion of the heat spreader is arranged between the two packaged chips rather than above the overlying chip, it provides a grounding plane to the package chips, so that the packaged chips would have better electrical performance during operation.